An active matrix substrate includes, for each pixel, a thin film transistor (hereinafter, “TFT”), for example, as a switching element. In the present specification, such a TFT is referred to as a “pixel TFT”. Amorphous silicon TFTs using an amorphous silicon film as the active layer and crystalline silicon TFTs using a crystalline silicon film such as a polycrystalline silicon film as the active layer have been used widely as pixel TFTs.
A part or whole of a peripheral driving circuit may be formed integrally on the same substrate as pixel TFTs. Such an active matrix substrate is called a driver-monolithic active matrix substrate. With a driver-monolithic active matrix substrate, the peripheral driving circuit is provided in a region (a non-display region or a bezel region) other than the region (the display region) including a plurality of pixels. The pixel TFTs and TFTs of the driving circuit (driving TFTs) can be formed by using the same semiconductor film. For example, a polycrystalline silicon film having a high field effect mobility is used as the semiconductor film.
It has been proposed to use an oxide semiconductor, instead of an amorphous silicon or a polycrystalline silicon, as the material of the active layer of the TFT. It has also been proposed to use an In—Ga—Zn—O-based semiconductor, whose main components are indium, gallium, zinc and oxygen, for example, as the oxide semiconductor. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has a higher mobility than an amorphous silicon. Therefore, an oxide semiconductor TFT is capable of operating faster than an amorphous silicon TFT. An oxide semiconductor film can be formed by a process that is simpler than that of a polycrystalline silicon film, and it can therefore be applied to devices that are required to have large surfaces.
With an oxide semiconductor TFT, if the gate electrode and the source or drain electrode overlap each other, as seen from a direction normal to the substrate, a gate-source parasitic capacitance and a gate-drain parasitic capacitance are formed in accordance with the area of overlap. If the parasitic capacitance is large, the operation speed of the oxide semiconductor TFT may lower.
In view of this, a TFT having a so-called offset structure has been proposed, in which the gate electrode and the source/drain electrode are arranged so as to be spaced apart from each other. In a TFT having an offset structure, a portion of the oxide semiconductor layer where the channel is formed (hereinafter referred to as the “channel formation region”) has a region (offset region) that does not overlap the gate electrode with the gate insulating film therebetween. In a channel-etch-type TFT, an “offset region” is a region of the channel formation region of the oxide semiconductor layer that overlaps none of the source electrode, the drain electrode and the gate electrode. Note that the “channel formation region” refers to a region of the oxide semiconductor layer that is located between the source contact region connected to the source electrode and the drain contact region connected to the drain electrode.
The offset region is a region that is not opposing the gate electrode and whose resistance is not lowered by the voltage application to the gate electrode. In a TFT having an offset structure, such an offset region is arranged in the channel formation region of the oxide semiconductor layer, thereby causing a problem that the ON current lowers. Particularly, an oxide semiconductor TFT has a good OFF leak characteristic while the resistance of the oxide semiconductor layer is often high. Therefore, if the distance between the gate electrode and the drain electrode is large, a sufficient ON characteristic may not be obtained in some cases.
In contrast, Patent Document No. 1, for example, discloses providing an auxiliary gate electrode so as to correspond to the offset region for the purpose of improving the electric characteristic of an oxide semiconductor TFT having an offset structure. In a bottom-gate-type oxide semiconductor TFT disclosed in Patent Document No. 1, an auxiliary gate electrode is arranged on the protective layer covering the TFT at a position that corresponds to the offset region of the oxide semiconductor layer.